Flexible Super Computer On-A-Chip
A revolutionary processor package that changes its architecture to adapt to the demands of different computing tasks exceeded all expectations in recent trials.
MONARCH: the architecture is flexible. (Credit: Image courtesy of USC Information Sciences Institute)
MONARCH (Morphable Networked Micro-Architecture) system designed by the USC Information Sciences Institute and Raytheon suits applications such as space radar and video processing, but also smart cars and highways, medical imaging, as well as GPS jamming for the military.
An ISI group headed by John Granacki developed the MONARCH architecture, working with the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems on a contract from DARPA.
Granacki is director of the Advanced Systems Division at ISI, and Research Associate Professor of Electrical Engineering Systems and Biomedical Engineering in the USC Viterbi School of Engineering.
“Polymorphic capability” and “super efficiency” are the key labels of the structure. “What we have been creating is essentially a supercomputer on a chip,” he said, “and not just a supercomputer, but a flexible supercomputer that reconfigures itself into the optimal supercomputer for each specific part of a multi-part task.”
This flexibility means MONARCH allows a significant reduction of the amount of hardware (and therefore power) required for computing systems, while still achieving extremely high (teraflop) throughput. Because of the memory integrated on the chip, very small systems may be implemented with only a single MONARCH device. For larger implementations, hardware demand is further reduced by MONARCH’s ability to “morph” devices to so they can perform downstream tasks instead of sitting idle while waiting for fresh input
In preliminary tests in the Phase III evaluation, a prototype system consisting of just one of the new devices provided sustained throughput of 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.
In power-efficiency “MONARCH outperformed the Intel quad-core Xeon chip by a factor of 10,” said Michael Vahey, Raytheon’s principal investigator for the project.